The present invention relates generally to a bipolar transistor and, more particularly, to a method for forming a bipolar transistor with a raised extrinsic base using a nitride pedestal and inner spacers to reduce emitter dimension, i.e., width.
Bipolar transistors are electronic devices with two p-n junctions that are in close proximity to each other. A typical bipolar transistor has three device regions: an emitter, a collector, and a base disposed between the emitter and the collector. If the emitter and collector are doped n-type and the base is doped p-type, the device is an xe2x80x9cnpnxe2x80x9d transistor. Alternatively, if the opposite doping configuration is used, the device is a xe2x80x9cpnpxe2x80x9d transistor. Because the mobility of minority carriers, i.e., electrons, in the base region of npn transistors is higher than that of holes in the base of pnp transistors, higher-frequency operation and higher-speed performances can be obtained with npn transistor devices. Therefore, npn transistors comprise the majority of bipolar transistors used to build integrated circuits.
As the vertical dimensions of the bipolar transistor are scaled more and more, serious device operational limitations have been encountered. One actively studied approach to overcome these limitations is to build transistors with emitter materials whose band gaps are larger than the band gaps of the material used in the base. Such structures are called heterojunction transistors.
Heterojunction bipolar transistors (HBTs) in which the emitter is formed of silicon (Si) and the base of a silicon-germanium (SiGe) alloy have recently been developed. The SiGe alloy (often expressed simply as silicon-germanium) is narrower in band gap than silicon.
The advanced silicon-germanium bipolar and complementary metal oxide semiconductor (BiCMOS) technology use a SiGe base in the heterojunction bipolar transistor. In the high-frequency (such as multi-GHz) regime, conventional compound semiconductors such as GaAs and InP currently dominate the market for high-speed wired and wireless communications. SiGe BiCMOS promises not only a comparable performance to GaAs in devices such as power amplifiers, but also a substantial cost reduction due to the use of standard Si IC fabrication processes and the integration of heterojunction bipolar transistors with standard CMOS.
Improving performance of HBTs involves reduction of carrier transmit time through the transistor and reduction of parasitics such as base resistance and collector-base capacitance. For high-performance HBT fabrication, yielding SiGe/Si HBTs, a conventional way to reduce the base resistance is through ion implantation into the extrinsic base. The ion implantation will cause damage, however, to regions that are in close proximity to the base region. Such damage induced base dopant diffusion and large parasitic capacitance associated with an implanted extrinsic base may ultimately lead to degradation in device performance.
To avoid implantation damage as well as large parasitic capacitance, a raised extrinsic base (Rext) is typically formed by depositing an extra layer of polycrystalline or single crystalline silicon (or SiGe) atop the conventional SiGe extrinsic base layer. There are essentially two processes that may be utilized to achieve such a raised extrinsic base. The first process involves selective epitaxy; the other involves chemical-mechanical polishing (CMP).
In a typical selective epitaxy process, the raised extrinsic base polycrystalline silicon is formed before the deposition of the intrinsic base SiGe. The intrinsic base SiGe is deposited selectively onto the exposed surface of silicon and polycrystalline silicon inside an over-hanging cavity structure. The selective epitaxy with a cavity structure mandates stringent process requirements for good selectivity, and suffers from poor process control. U.S. Pat. No. 5,523,606 to Yamazaki and U.S. Pat. No. 5,620,908 to Inoh, et al. are some examples of prior art selective epitaxy processes.
As mentioned above, CMP can be applied to form a raised extrinsic base. U.S. Pat. No. 5,015,594 to Chu et al. discloses the formation of extrinsic base polysilicon by CMP. The isolation, which is achieved by thermal oxidation, is not feasible in high performance devices due to the high temperature thermal process.
U.S. Pat. No. 6,492,238 to Ahlgren, et al. provides a self-aligned process for forming a bipolar transistor with a raised extrinsic base, an emitter, and a collector integrated with a complementary metal oxide semiconductor (CMOS) circuit with a gate. An intermediate semiconductor structure is provided having a CMOS area and a bipolar area. An intrinsic base layer is provided in the bipolar area. A base oxide is formed across, and a sacrificial emitter stack of silicon layer is deposited on both the CMOS and bipolar areas. A photoresist is applied to protect the bipolar area and the structure is etched to remove the emitter stack silicon layer from the CMOS area only such that the top surface of the emitter stack silicon layer on the bipolar area is substantially flush with the top surface of the CMOS area. Finally, a polish stop layer is deposited having a substantially flat top surface across both the CMOS and bipolar areas suitable for subsequent chemical-mechanical polishing (CMP).
Self-aligned processes such as the one disclosed in the xe2x80x3238 patent minimize the distance between the extrinsic base and the intrinsic base. Reduction of intrinsic base sheet resistance helps to reduce the total base resistance, but there is a trade off between low base sheet resistance and long carrier base transit time. To further lower the base resistance, one can also decrease the emitter width, which functions to reduce the intrinsic base resistance. However, forming ultra-narrow emitters usually requires advanced lithographic tools or advanced photomasks such as phase shift masks, which significantly increases the overall cost of fabricating high-performance raised extrinsic base HBTs.
In view of the drawbacks mentioned above with fabricating high-performance HBTs having reduced carrier transit time, there is a need for providing a method of fabricating a HBT having a raised extrinsic base and a narrow emitter dimension, i.e., width.
One object of the present invention is to provide a simple, yet reliable method of fabricating a high-performance HBT.
A further object of the present invention is to provide a method of fabricating a high-speed and high-performance HBT having a raised extrinsic base.
A yet further object of the present invention is to provide a method of fabricating a HBT having a narrow emitter dimension, i.e., width, in which advanced lithographic tools and/or advanced photomasks are not required.
These and other objects and advantages are achieved in the present invention by providing and utilizing a nitride pedestal in a self-aligned process in which inner spacers are employed to reduce the area for fabricating an emitter. In the present method, outer spacers are not employed to separate the polysilicon in the emitter pedestal from the raised extrinsic base. Thus, the method of the present invention can effectively reduce the final emitter dimension. The method of the present invention achieves narrow emitter dimension (in the present application the terms emitter dimension and emitter width are interchangeably used; for the sake of clarity the remaining portions of the application will only use the term emitter width) without the need of advanced lithographic tools and/or advanced photomasks such as phase shift masks. Another advantage of the method of the present invention is that it has fewer processing steps as compared with prior art self-aligned processes.
One aspect of the present invention is directed to a method of fabricating a high-performance, raised extrinsic base HBT having a narrow emitter width that includes the steps of:
providing a structure comprising a patterned nitride pedestal region which exposes a portion of an underlying base region;
forming a stack comprises at least a bottom doped semiconducting layer on the exposed portion of the base region;
selectively removing the patterned nitride pedestal region to provide an opening for an emitter having a first width;
forming inner spacers in the opening to provide a second width that is less than the first width; and
forming an emitter in the opening.
In the present invention, the base region includes a monocrystalline region that is surrounded on either side by adjoining polycrystalline regions. The monocrystalline region is formed atop a Si substrate, whereas the polycrystalline regions are located atop trench isolation regions that are located in the Si substrate.